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XR-2211A
...the analog plus company TM
FSK Demodulator/ Tone Decoder
September 1996-4
FEATURES D Wide Frequency Range D Wide Supply Voltage Range 0.01Hz to 300kHz 4.5V to 20V
APPLICATIONS D Caller Identification Delivery D FSK Demodulation D Data Synchronization D Tone Decoding D FM Detection D Carrier Detection
D HCMOS/TTL/Logic Compatibility D FSK Demodulation, with Carrier Detection D Wide Dynamic Range D Excellent Temp. Stability 10mV to 3V rms 100 ppm/C, typ. D Adjustable Tracking Range (+1% to 80%)
GENERAL DESCRIPTION The XR-2211A is a monolithic phase-locked loop (PLL) system especially designed for data communications applications. It is particularly suited for FSK modem applications. It operates over a wide supply voltage range of 4.5 to 20V and a wide frequency range of 0.01Hz to 300kHz. It can accommodate analog signals between 10mV and 3V, and can interface with conventional DTL, TTL, and ECL logic families. The circuit consists of a basic PLL for tracking an input signal within the pass band, a quadrature phase detector which provides carrier detection, and an FSK voltage comparator which provides FSK demodulation. External components are used to independently set center frequency, bandwidth, and output delay. An internal voltage reference proportional to the power supply is provided at an output pin. The XR-2211A is available in 14 pin packages specified for commercial temperature ranges.
ORDERING INFORMATION
Part No. XR-2211ACP XR-2211ACD
Package 14 Lead PDIP (0.300") 14 Lead SOIC (Jedec, 0.150")
Operating Temperature Range 0C to +70C 0C to +70C
Rev. 1.01
E1995
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
XR-2211A
BLOCK DIAGRAM
VCC 1 GND 4 NC 9
Pre Amplifier INP 2 Loop 0-Det Lock Detect Comparator
11 3
LDO LDF
TIM C1
14
VCO TIM C2 TIM R VREF COMP I 13 12 Internal 10 8 VREF Reference FSK Comp Quad 0-Det
6
LDOQ
5
LDOQN
7
DO
Figure 1. XR-2211A Block Diagram
Rev. 1.01 2
XR-2211A
PIN CONFIGURATION
VCC INP LDF GND LDOQN LDOQ DO
1 2 3 4 5 6 7 14 13 12 11 10 9 8
TIM C1 TIM C2 TIM R LDO VREF NC COMP I
VCC INP LDF GND LDOQN LDOQ DO
1 2 3 4 5 6 7
14 13 12 11 10 9 8
TIM C1 TIM C2 TIM R LDO VREF NC COMP I
14 Lead PDIP (0.300")
14 Lead SOIC (Jedec, 0.150")
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol VCC INP LDF GND LDOQN LDOQ DO COMP I NC VREF LDO TIM R TIM C2 TIM C1 Type I O O O O I O O I I I Description Positive power supply. Receive Analog Input. Lock detect filter. Ground pin. Lock detect output not. This output will be low if the VCO is in the capture range. Lock detect output. This output will be high if the VCO is in the capture range. Data output. Decoded FSK output. FSK Comparator Input. Not connected. Internal voltage reference. The value of VREF is VCC/2 - 650mV. Loop detect output. This output provides the result of the quadrature phase detection. Timing resistor input. This pin connects to the timing resistor of the VCO. Timing capacitor input. The timing capacitor connects between this pin and pin 14. Timing capacitor input. The timing capacitor connects between this pin and pin 13.
Rev. 1.01 3
XR-2211A
DC ELECTRICAL CHARACTERISTICS
Test Conditions: VCC = 12V, TA = +25C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter GENERAL Supply Voltage Supply Current Oscillator Section Frequency Accuracy Frequency Stability Temperature Power Supply Upper Frequency Limit Lowest Practical Operating Frequency Timing Resistor, R0 - See Figure 5. Operating Range Recommended Range Loop Phase Dectector Section Peak Output Current Output Offset Current Output Impedance Maximum Swing Quadrature Phase Detector Peak Output Current Output Impedance Maximum Swing Input Preampt Section Input Impedance Input Signal Voltage Required to Cause Limiting 2 mVrms 20 KW 300 1 11 mA MW VPP Measured at pin 2 +4 +100 +200 +2 1 +5 +300 mA mA MW V Referenced to Pin 10 Measured at Pin 3 Measured at Pin 11 5 5 2000 100 KW KW See Figure 7. and Figure 8. 0.01 Hz R0 = 2MW, C0 = 50WF +100 0.25 0.2 300 ppm/C %/V %/V kHz * See Figure 8. VCC = 12 + 1V. See Figure 7. VCC = + 5.0V. See Figure 7. R0 = 8.2kW, C0 = 400pF +3 % Deviation from fO = 1/R0 C0 4.5 5 20 9 V mA R0 > 10kW. See Figure 4. Min. Typ. Max. Unit Conditions
Note: - These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. - Bold face parameters are covered by production test.
Rev. 1.01 4
XR-2211A
DC ELECTRICAL CHARACTERISTICS (Cont.)
Test Conditions: VCC = 12V, TA = +25C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter Voltage Comparator Section Input Impedance Input Bias Current Voltage Gain Output Voltage Low Output Leakage Current Internal Reference Voltage Level Output Impedance Maximum Source Current 4.75 5.3 100 80 5.85 V W mA Measured at pin 10 AC Small Signal 55 2 100 70 300 0.01 500 10 MW nA dB mV mA RL = 5.1KW IC = 3mA VO = 20V Measured at pins 3 and 8 Min. Typ. Max. Unit Conditions
Note: - These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. - Bold face parameters are covered by production test.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 900mW Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . 800mW Derate Above TA = +25C . . . . . . . . 6mW/C JEDEC SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . 390mW Derate Above TA = +25C . . . . . . . . . 5mW/C
SYSTEM DESCRIPTION The main PLL within the XR-2211A is constructed from an input preamplifier, analog multiplier used as a phase detector and a precision voltage controlled oscillator (VCO). The preamplifier is used as a limiter such that input signals above typically 10mV RMS are amplified to a constant high level signal. The multiplying-type phase detector acts as a digital exclusive or gate. Its output (unfiltered) produces sum and difference frequencies of the input and the VCO output. The VCO is actually a current controlled oscillator with its normal input current (fO) set by a resistor (R0) to ground and its driving current with a resistor (R1) from the phase detector. The output of the phase detector produces sum and difference of the input and the VCO frequencies
Rev. 1.01 5
(internally connected). When in lock, these frequencies are fIN+ fVCO (2 times fIN when in lock) and fIN - fVCO (0Hz when lock). By adding a capacitor to the phase detector output, the 2 times fIN component is reduced, leaving a DC voltage that represents the phase difference between the two frequencies. This closes the loop and allows the VCO to track the input frequency. The FSK comparator is used to determine if the VCO is driven above or below the center frequency (FSK comparator). This will produce both active high and active low outputs to indicate when the main PLL is in lock (quadrature phase detector and lock detector comparator).
XR-2211A
PRINCIPLES OF OPERATION Signal Input (pin 2): Signal is AC coupled to this terminal. The internal impedance at pin 2 is 20KW. Recommended input signal level is in the range of 10mV rms to 3V rms. Quadrature Phase Detector Output (pin 3): This is the high impedance output of quadrature phase detector and is internally connected to the input of lock detect voltage comparator. In tone detection applications, pin 3 is connected to ground through a parallel combination of RD and CD (see Figure 3.) to eliminate the chatter at lock detect outputs. If the tone detect section is not used, pin 3 can be left open. Lock Detect Output, Q (pin 6): The output at pin 6 is at "low" state when the PLL is out of lock and goes to "high" state when the PLL is locked. It is an open collector type output and requires a pull-up resistor, RL, to VCC for proper operation. At "low" state, it can sink up to 5mA of load current. Lock Detect Complement, (pin 5): The output at pin 5 is the logic complement of the lock detect output at pin 6. This output is also an open collector type stage which can sink 5mA of load current at low or "on" state. FSK Data Output (pin 7): This output is an open collector logic stage which requires a pull-up resistor, RL, to VCC for proper operation. It can sink 5mA of load current. When decoding FSK signals, FSK data output is at "high" or "off" state for low input frequency, and at "low" or "on" state for high input frequency. If no input signal is present, the logic state at pin 7 is indeterminate. FSK Comparator Input (pin 8): This is the high impedance input to the FSK voltage comparator. Normally, an FSK post-detection or data filter is connected between this terminal and the PLL phase detector output (pin 11). This data filter is formed by RF and CF (see Figure 3.). The threshold voltage of the comparator is set by the internal reference voltage, VREF, available at pin 10. Reference Voltage, VREF (pin 10): This pin is internally biased at the reference voltage level, VREF: VREF = VCC /2 - 650mV. The DC voltage level at this pin forms an internal reference for the voltage levels at pins 5, 8, 11 and 12. Pin 10 must be bypassed to ground with a 0.1mF capacitor for proper operation of the circuit.
Rev. 1.01 6
Loop Phase Detector Output (pin 11): This terminal provides a high impedance output for the loop phase detector. The PLL loop filter is formed by R1 and C1 connected to pin 11 (see Figure 3.). With no input signal, or with no phase error within the PLL, the DC level at pin 11 is very nearly equal to VREF. The peak to peak voltage swing available at the phase detector output is equal to 2 x VREF. VCO Control Input (pin 12): VCO free-running frequency is determined by external timing resistor, R0, connected from this terminal to ground. The VCO free-running frequency, fO, is:
fO +
1 Hz R 0*C 0
where C0 is the timing capacitor across pins 13 and 14. For optimum temperature stability, R0 must be in the range of 10KW to 100KW (see Figure 9.). This terminal is a low impedance point, and is internally biased at a DC level equal to VREF. The maximum timing current drawn from pin 12 must be limited to < 3mA for proper operation of the circuit. VCO Timing Capacitor (pins 13 and 14): VCO frequency is inversely proportional to the external timing capacitor, C0, connected across these terminals (see Figure 6.). C0 must be non-polar, and in the range of 200pF to 10mF. VCO Frequency Adjustment: VCO can be fine-tuned by connecting a potentiometer, RX, in series with R0 at pin 12 (see Figure 10.). VCO Free-Running Frequency, fO: XR-2211A does not have a separate VCO output terminal. Instead, the VCO outputs are internally connected to the phase detector sections of the circuit. For set-up or adjustment purposes, the VCO free-running frequency can be tuned by using the generalized circuit in Figure 3., and applying an alternating bit pattern of O's and 1's at the known mark and space frequencies. By adjusting R0, the VCO can then be tuned to obtain a 50% duty cycle on the FSK output (pin 7). This will ensure that the VCO fO value is accurately referenced to the mark and space frequencies.
XR-2211A
Input
Figure 2. Functional Block Diagram of a Tone and FSK Decoding System Using XR-2211A
Input Signal 0.1mF
2
Rev. 1.01 7
II III IIIIII II IIIIII II IIIIII III III III III IIIII IIIIII IIIII IIIIII IIIII IIIIII
Det VCO Preamp Det Lock Detect Filter Lock Detect Comp Loop Phase Detect 11 C1 RF 8 CF R1 VCO 14 C0 Quad Phase Detect 12 0.1mF 13 R0 10 3 RD CD
Loop Filter
Data Filter
FSK Output
FSK Comp
Lock Detect Outputs
VCC RB Rl 7 FSK Comp. Internal Reference
6 LDOQ LDOQN Lock Detect Comp. 5
Figure 3. Generalized Circuit Connection for FSK and Tone Detection
XR-2211A
DESIGN EQUATIONS (All resistance in W, all frequency in Hz and all capacitance in farads, unless otherwise specified) (See Figure 3. for definition of components) 1. VCO Center Frequency, fO:
fO +
1 R 0*C 0
2. Internal Reference Voltage, VREF (measured at pin 10):
V REF +
V CC 2
-650mV in volts
3. Loop Low-Pass Filter Time Constant, t: t + C 1*R PP (seconds) where:
R PP +
R 1*R F R1 ) RF
if RF is 1 or CF reactance is 1, then RPP = R1 4. Loop Damping, j: z+ 1250*C 0 R 1*C 1
Note: For derivation/explanation of this equation, please see TAN-011.
5. Loop-tracking Df bandwidth, "+ f 0 Df + R 0 R1 f0
Tracking Bandwidth Df Df
fLL
f1
fO
f2
fLH
Rev. 1.01 8
XR-2211A
6. FSK Data filter time constant, tF: tF +
RB * RF *C (seconds) ( R B ) R F) F
7. Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage across pin 10 and pin11, per unit of phase error at phase detector input):
Kd +
V REF * R 1 volt 10, 000*p radian
Note: For derivation/explanation of this equation, please see TAN-011.
8. VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit of DC voltage change at pin 11):
K0 +
-2p + V REF *C 0 * R 1
radian second volt
9. The filter transfer function:
F(s) +
1 at 0 Hz. 1 ) SR 1*C 1
S = Jw and w = 0
10. Total loop gain. KT:
K T + K O*K d*F(s) +
11. Peak detector current IA:
RF 5, 000*C 0*(R 1 ) R F)
1 seconds
IA +
V REF (V REF in volts and I A in amps) 20, 000
Note: For derivation/explanation of this equation, please see TAN-011.
Rev. 1.01 9
XR-2211A
APPLICATIONS INFORMATION FSK Decoding
Figure 10. shows the basic circuit connection for FSK decoding. With reference to Figure 3. and Figure 10., the functions of external components are defined as follows: R0 and C0 set the PLL center frequency, R1 sets the system bandwidth, and C1 sets the loop filter time constant and the loop damping factor. CF and RF form a one-pole post-detection filter for the FSK data output. The resistor RB from pin 7 to pin 8 introduces positive feedback across the FSK comparator to facilitate rapid transition between output logic states.
Design Instructions: The circuit of Figure 10. can be tailored for any FSK decoding application by the choice of five key circuit components: R0, R1, C0, C1 and CF. For a given set of FSK mark and space frequencies, fO and f1, these parameters can be calculated as follows: (All resistance in W's, all frequency in Hz and all capacitance in farads, unless otherwise specified) a) Calculate PLL center frequency, fO:
f O + F 1*F 2
b) Choose value of timing resistor R0, to be in the range of 10KW to 100KW. This choice is arbitrary. The recommended value is R0 = 20KW. The final value of R0 is normally fine-tuned with the series potentiometer, RX.
RO + RO )
RX 2
c) Calculate value of C0 from design equation (1) or from Figure 7.:
CO +
1 R0 * f0
d) Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R1 +
R 0*f 0 *2 (f 1-f 2)
e) Calculate C1 to set loop damping. (See design equation 4): Normally, j = 0.5 is recommended.
C1 +
1250*C 0 R1 * j2
Rev. 1.01 10
XR-2211A
f) The input to the XR-2211A may sometimes be too sensitive to noise conditions on the input line. Figure 4. illustrates a method of de-sensitizing the XR-2211A from such noisy line conditions by the use of a resistor, Rx, connected from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level.
V IN minimum (peak) + V a-V b + DV " 2.8mV offset + V REF
V 20, 000 or R X + 20, 000 REF -1 (20, 000 ) R X) DV
VIN minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold)
Vcc
To Phase Detector Input
Rx
VREF 10
Figure 4. Desensitizing Input Stage
g) Calculate Data Filter Capacitance, CF:
R sum +
(R F ) R 1)*R B (R 1 ) R F ) R B) 1 . seconds
CF +
250 R sum*(Baud Rate)
Note: All values except R0 can be rounded to nearest standard value.
Rev. 1.01 11
II II
2
Va
Vb
20K
20K
II II
Baud rate in
XR-2211A
Supply vs. Current (mA)
15 R0=5K 10 R0=10K 5 R0>100K 0 4 6 8 10 12 14 16 18 20 22 24 Supply Voltage, V+ (Volts) C 0( mF)
0.1
0.01 100
Figure 5. Typical Supply Current vs. V+ (Logic Outputs Open Circuited)
Figure 6. VCO Frequency vs. Timing Resistor
1.02 Normalized Frequency 1.01 1.00 0.99 0.98 0.97
C0=0.0033mF
100
C0=0.01mF
C0=0.1mF
C0=0.0331mF
10
C0=0.33mF
0
1000 fO(Hz)
10000
Figure 7. VCO Frequency vs. Timing Capacitor
Normalized Frequency Drift (% of f O) +1.0 R0=10K +0.5 500K 0 R0=50K 50K R0=500K -0.5 R0=1M -1.0 -50 -25 0 25 V+ = 12V R1 = 10 R0 fO = 1 kHz 50 75 100 125 10K 1M
Temperature (C)
Figure 9. Typical Center Frequency Drift vs. Temperature
Rev. 1.01 12
IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIII
IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII
1,000
C0=0.001mF
R0 (K )
IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII IIIIIIIIIII
R0=5KW R0=10KW R0=20KW R0=40KW R0=80KW R0=160KW 1000 fO(HZ) 10000 5 fO = 1kHz RF = 10R0 1 5 4 2 4 3 3 2 1 4 6 8 10 12 14 R0 Curve 1 5K 2 10K 3 30K 4 100K 300K 5 16 18 20 22 24 V+ (Volts)
20
1.0
Figure 8. Typical fO vs. Power Supply Characteristics
XR-2211A
Design Example:
1200 Baud FSK demodulator with mark and space frequencies of 1200/2200. Step 1: Calculate fO: from design instructions (a) f O + 1200*2200 =1624 Step 2: Calculate R0 : R0 =10K with a potentiometer of 10K. (See design instructions (b)) (b) R T + 10 ) 10 + 15K 2 Step 3: Calculate C0 from design instructions (c) C O + 1 + 39nF 15000*1624
Step 4: Calculate R1 : from design instructions (d) R 1 + 20000*1624*2 + 51, 000 (2200-1200) Step 5: Calculate C1 : from design instructions (e) C 1 + 1250*39nF + 3.9nF 51000*0.5 2 Step 6: Calculate RF : RF should be at least five times R1, RF = 51,0005 = 255 KW Step 7: Calculate RB : RB should be at least five times RF, RB = 255,0005 = 1.2 MW Step 8: Calculate RSUM : (R F ) R 1)*R B + 240KW (R F ) R 1 ) R B)
R SUM +
Step 9: Calculate CF :
CF +
250 R SUM*Baud Rate
+ 1nF
Note: All values except R0 can be rounded to nearest standard value.
Rev. 1.01 13
XR-2211A
VCC RB Loop Phase Detect 11 C1 2.7nF 5% VCO 14 27nF 13 CO 5% Rx 20K 12 RF 178K 5% 1nF R1 35.2K 1% 0.1F R0 20K 1% VCO Fine Tune 6 Quad Phase Detect LDOQ LDOQN Lock Detect Comp. 5 8 1.8m 5% 7 FSK Comp. Internal Reference RL 5.1K 5% Data Output
CF 10% 10
Input Signal
2 0.1F
Figure 10. Circuit Connection for FSK Decoding of Caller Identification Signals (Bell 202 Format)
VCC RB Loop Phase Detect 11 C1 R1 0.1F 13 C0 Rx 6 LDOQ Quad Phase Detect RD Between 400K And 600K R0 RF 8 CF 10 7 FSK Comp. Internal Reference RL 5.1k
Input Signal 0.1F
2 14
VCO
12
3 CD
Lock Detect Comp.
5 LDOQN
Figure 11. External Connectors for FSK Demodulation with Carrier Detect Capability
Rev. 1.01 14
XR-2211A
VCC Loop Phase Detect 11 C1 220pF 5% 12 VCO 14 13 C0 5% 50nF 8 7 FSK Comp. Internal Reference VCC VCO Fine Tune 6 LDOQ Quad Phase Detect
2 0.1F Tone Input
R1 200K 10 1% 0.1F R0 20K 1% Rx 5K
RL2 5.1K
RL3 5.1K Logic Output
3 RD 470K CD 80nF
5 LDOQN Lock Detect Comp.
Figure 12. Circuit Connection for Tone Detection FSK Decoding with Carrier Detect The lock detect section of XR-2211A can be used as a carrier detect option for FSK decoding. The recommended circuit connection for this application is shown in Figure 11. The open collector lock detect output, pin 6, is shorted to data output (pin 7). Thus, data output will be disabled at "low" state, until there is a carrier within the detection band of the PLL and the pin 6 output goes "high" to enable the data output.
Note: Data Output is "Low" When No Carrier is Present.
frequency approaches the capture bandwidth. Excessively large values of CD will slow the response time of the lock detect output. For Caller I.D. applications choose CD = 0.1mF. Tone Detection
The minimum value of the lock detect filter capacitance CD is inversely proportional to the capture range, +Dfc. This is the range of incoming frequencies over which the loop can acquire lock and is always less than the tracking range. It is further limited by C1. For most applications, Dfc > Df/2. For RD = 470KW, the approximate minimum value of CD can be determined by:
Figure 12. shows the generalized circuit connection for tone detection. The logic outputs, LDOQN and LDOQ at pins 5 and 6 are normally at "high" and "low" logic states, respectively. When a tone is present within the detection band of the PLL, the logic state at these outputs become reversed for the duration of the input tone. Each logic output can sink 5mA of load current.
Both outputs at pins 5 and 6 are open collector type stages, and require external pull-up resistors RL2 and RL3, as shown in Figure 12. With reference to Figure 3. and Figure 12., the functions of the external circuit components can be explained as follows: R0 and C0 set VCO center frequency; R1 sets the detection bandwidth; C1 sets the low pass-loop filter time constant and the loop damping factor.
C D 16 C in mF and f in Hz. Df
C in mF and f in Hz. With values of CD that are too small, chatter can be observed on the lock detect output as an incoming signal
Rev. 1.01 15
XR-2211A
Design Instructions: The circuit of Figure 12. can be optimized for any tone detection application by the choice of the 5 key circuit components: R0, R1, C0, C1 and CD. For a given input, the tone frequency, fS, these parameters are calculated as follows: (All resistance in W's, all frequency in Hz and all capacitance in farads, unless otherwise specified) a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min. current that the internal voltage reference can deliver. The recommended value is R0 = 20KW. The final value of R0 is normally fine-tuned with the series potentiometer, RX. b) Calculate value of C0 from design equation (1) or from Figure 7. fS = fO:
CO +
1 R 0*fs
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0*f 0*2 Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C1 for a given loop damping factor: Normally, j = 0.5 is recommended.
C1 +
1250*C 0 R 1*j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time. e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D 16 Df
C in mF
Increasing CD slows down the logic output response time. Design Examples: Tone detector with a detection band of + 100Hz: a) Choose value of timing resistor R0 to be in the range of 10KW to 50KW. This choice is dictated by the max./min. current that the internal voltage reference can deliver. The recommended value is R0 = 20 KW. The final value of R0 is normally fine-tuned with the series potentiometer, RX. b) Calculate value of C0 from design equation (1) or from Figure 6. fS = fO:
C0 +
1+ 1 + 50nF 20, 000*1, 000 R 0*f S
Rev. 1.01 16
XR-2211A
c) Calculate R1 to set the bandwidth +Df (See design equation 5):
R1 +
R 0*f O*2 20, 000*1, 000*2 + + 400K 100 Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C0 for a given loop damping factor: Normally, j = 0.5 is recommended.
C1 +
-9 1250*C 0 + 1250*50*10 2 + 6.25pF 400, 000*0.5 R 1*j 2
Increasing C1 improves the out-of-band signal rejection, but increases the PLL capture time. e) Calculate value of the filter capacitor CD . To avoid chatter at the logic output, with RD = 470KW, CD must be:
C D + 16 w 16 w 80nF 200 Df
Increasing CD slows down the logic output response time. f) Fine tune center frequency with 5KW potentiometer, RX.
VCC VCC RF 100K Loop Phase Detect 11 C1 R1 0.1F R0 6 LDOQ LDOQN Lock Detect Comp. 5 10 8 3 7 FSK Comp . Internal Reference CF 2 1 1 4 1 LM324 Demodulated Output 0.1F
2 0.1F FM Input 14
VCO 13 C0 Quad Phase Detect
12
Figure 13. Linear FM Detector Using XR-2211A and an External Op Amp. (See Section on Design Equation for Component Values.)
Rev. 1.01 17
XR-2211A
Linear FM Detection XR-2211A can be used as a linear FM detector for a wide range of analog communications and telemetry applications. The recommended circuit connection for this application is shown in Figure 13. The demodulated output is taken from the loop phase detector output (pin 11), through a post-detection filter made up of RF and CF, and an external buffer amplifier. This buffer amplifier is necessary because of the high impedance output at pin 11. Normally, a non-inverting unity gain op amp can be used as a buffer amplifier, as shown in Figure 13. The FM detector gain, i.e., the output voltage change per unit of FM deviation can be given as:
V OUT +
R 1*V REF 100*R 0
where VR is the internal reference voltage (VREF = VCC /2 - 650mV). For the choice of external components R1, R0, CD, C1 and CF, see the section on design equations.
V+ 1 20K REF Voltage Output Input 2 10 10K 20K 10K
B From VCO B'
Lock Detect Filter 3 6 Lock Detect Outputs 5
Internal Voltage Reference
Input Preamplifier and Limiter
Quadrature Phase Detector
Lock Detect Comparator
2K
2K
8 A Timing Capacitor 13 C0 14 B' B A' A From VCO A' 11 FSK Comparator Loop Input Detector Output
7 FSK Data Output
4 Ground
12 R0 Timing Resistor Voltage Controlled Oscillator
8K
Loop Phase Detector
FSK Comparator
Figure 14. Equivalent Schematic Diagram
Rev. 1.01 18
XR-2211A
14 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
Rev. 1.00
14 1 D
8 7 E1 E A2
Seating Plane
A L A1 B e B1
eA eB
C
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.725 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 0.795 0.325 0.280
MILLIMETERS MIN 3.68 0.38 2.92 0.36 0.76 0.20 18.42 7.62 6.10 MAX 5.33 1.78 4.95 0.56 1.78 0.38 20.19 8.26 7.11
0.100 BSC 0.300 BSC 0.310 0.115 0 0.430 0.160 15
2.54 BSC 7.62 BSC 7.87 2.92 0 10.92 4.06 15
Note: The control dimension is the inch column
Rev. 1.01 19
XR-2211A
14 LEAD SMALL OUTLINE (150 MIL JEDEC SOIC)
Rev. 1.00
D
14
8
E
1 7
H
C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H L MIN 0.053 0.004 0.013 0.007 0.337 0.150 MAX 0.069 0.010 0.020 0.010 0.344 0.157
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00
0.050 BSC 0.228 0.016 0.244 0.050
1.27 BSC 5.80 0.40 6.20 1.27 8
0 8 0 Note: The control dimension is the millimeter column
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XR-2211A Notes
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XR-2211A Notes
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XR-2211A Notes
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XR-2211A
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1995 EXAR Corporation Datasheet September 1996 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.01 24

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